HC & HCT families | LS family | Open collector outputs
Gates: 2-input | 3-input |
4-input | 8-input | NOT
Decade and 4-bit counters: 7490 | 7493 | 74390 |
74393 | 74160-3 | 74192-3 |
74HC4017
12-bit and 14-bit counters: 74HC4020 | 74HC4040 |
74HC4060
Decoders & display drivers: 7442 | 7447 |
74HC4511
Also see: 4000 Series | Logic Gates |
Counting Circuits |
ICs (chips) (with summary of logic ICs)
Quick links to individual ICs
7400 7432 |
The 74LS (Low-power Schottky) family (like the original) uses TTL (Transistor-Transistor Logic) circuitry which is fast but requires more power than later families. The 74 series is often still called the 'TTL series' even though the latest chips do not use TTL!
The 74HC family has High-speed CMOS circuitry, combining the speed of TTL with the very low power consumption of the 4000 series. They are CMOS chips with the same pin arrangements as the older 74LS family. Note that 74HC inputs cannot be reliably driven by 74LS outputs because the voltage ranges used for logic 0 are not quite compatible, use 74HCT instead.
The 74HCT family is a special version of 74HC with 74LS TTL-compatible inputs so 74HCT can be safely mixed with 74LS in the same system. In fact 74HCT can be used as low-power direct replacements for the older 74LS ICs in most circuits. The minor disadvantage of 74HCT is a lower immunity to noise, but this is unlikely to be a problem in most situations.
The CMOS circuitry used in the 74HC and 74HCT series ICs means that they are static sensitive. Touching a pin while charged with static electricity (from your clothes for example) may damage the IC. In fact most ICs in regular use are quite tolerant and earthing your hands by touching a metal water pipe or window frame before handling them will be adequate. ICs should be left in their protective packaging until you are ready to use them.
To compare the different logic families please see the Summary table of logic families
For most new projects the 74HC family is the best choice.
The 74LS and 74HCT families require a 5V supply so they are not convenient for battery operation.
74HC and 74HCT family characteristics:
74LS family TTL characteristics:
Note that 74HC inputs cannot be reliably driven by 74LS outputs because the
voltage ranges used for logic 0 are not quite compatible. For reliability use
74HCT if the system includes some 74LS chips.
The diagram shows how an open collector output can be connected to sink current from a supply which has a higher voltage than the logic IC supply. The maximum load supply is 15V for most open collector ICs.
Open collector outputs can be safely connected together to switch on a load when any one of them is low;
unlike normal outputs which must be combined using diodes.
There are many ICs in the 74 series and this page only covers a selection,
concentrating on the most useful gates, counters,
decoders and display drivers.
For each IC there is a diagram showing the pin arrangement and brief notes explain
the function of the pins where necessary.
For simplicity the family letters after the 74 are omitted in the diagrams below
because the pin connections apply to all 74 series gates with the same number.
For example 7400 NAND gates are available as 74HC00, 74HCT00 and 74LS00.
If you are using another reference please be aware that there is some variation in the terms used to describe pin functions, for example reset is also called clear. Some inputs are 'active low' which means they perform their function when low. If you see a line drawn above a label it means it is active low, for example: (say 'reset-bar').
Datasheets are available from:
NC = No Connection (a pin that is not used).
NC = No Connection (a pin that is not used). # on the 7490 pins 6 and 7 connect to an internal AND gate for resetting to 9. For normal use connect QA to clockB and |
The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain.
The counter is in two sections: clockA-QA and clockB-QB-QC-QD. For normal use connect QA to clockB to link the two sections, and connect the external clock signal to clockA.
For normal operation at least one reset0 input should be low, making both high resets the counter to zero (0000, QA-QD low). Note that the 7490 has a pair of reset9 inputs on pins 6 and 7, these reset the counter to nine (1001) so at least one of them must be low for counting to occur.
Counting to less than the maximum (9 or 15) can be achieved by connecting the appropriate output(s) to the two reset0 inputs. If only one reset input is required the two inputs can be connected together. For example: to count 0 to 8 connect QA (1) and QD (8) to the reset inputs.
Connecting ripple counters in a chain: please see 74393 below.
For normal use connect QA to clockB and connect the external clock signal to clockA. |
The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain.
Each counter is in two sections: clockA-QA and clockB-QB-QC-QD. For normal use connect QA to clockB to link the two sections, and connect the external clock signal to clockA.
For normal operation the reset input should be low, making it high resets the counter to zero (0000, QA-QD low).
Counting to less than 9 can be achieved by connecting the appropriate output(s) to the reset input, using an AND gate if necessary. For example: to count 0 to 7 connect QD (8) to reset, to count 0 to 8 connect QA (1) and QD (8) to reset using an AND gate.
Connecting ripple counters in a chain: please see 74393 below.
The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means means a counter output can directly drive the clock input of the next counter in a chain.
For normal operation the reset input should be low, making it high resets the counter to zero (0000, QA-QD low).
Counting to less than 15 can be achieved by connecting the appropriate output(s) to the reset input,
using an AND gate if necessary. For example to count 0 to 8 connect QA (1) and QD (8) to reset using an AND gate.
Connecting ripple counters in a chain
The diagram below shows how to link ripple counters in a chain, notice how the highest output QD of each
counter drives the clock input of the next counter.
* reset and preset are both active-low preset is also known as parallel enable (PE) |
The count advances as the clock input becomes high (on the rising-edge). The decade counters count from 0 to 9 (0000 to 1001 in binary). The 4-bit counters count from 0 to 15 (0000 to 1111 in binary).
For normal operation (counting) the reset, preset, count enable and carry in inputs should all be high. When count enable is low the clock input is ignored and counting stops.
The counter may be preset by placing the desired binary number on the inputs A-D, making the preset input low, and applying a positive pulse to the clock input. The inputs A-D may be left unconnected if not required.
The reset input is active-low so it should be high (+Vs) for normal operation (counting). When low it resets the count to zero (0000, QA-QD low), this happens immediately with the 74160 and 74161 (standard reset), but with the 74162 and 74163 (synchronous reset) the reset occurs on the rising-edge of the clock input.
Counting to less than the maximum (15 or 9) can be achieved by connecting the appropriate output(s) through a NOT or NAND gate to the reset input. For the 74162 and 74163 (synchronous reset) you must use the output(s) representing one less than the reset count you require, e.g. to reset on 7 (counting 0 to 6) use QB (2) and QC (4).
Connecting synchronous counters in a chain
The diagram below shows how to link synchronous counters such as 74160-3, notice how all the
clock (CK) inputs are linked. Carry out (CO) is used to feed the carry in (CI)
of the next counter. Carry in (CI) of the first 74160-3 counter should be high.
* preset is active-low |
These counters have separate clock inputs for counting up and down. The count increases as the up clock input becomes high (on the rising-edge). The count decreases as the down clock input becomes high (on the rising-edge). In both cases the other clock input should be high.
For normal operation (counting) the preset input should be high and the reset input low. When the reset input is high it resets the count to zero (0000, QA-QD low)
The counter may be preset by placing the desired binary number on the inputs A-D and briefly
making the preset input low. Note that a clock pulse is not required to preset, unlike the 74160-3 counters.
The inputs A-D may be left unconnected if not required.
Connecting counters with separate up and down clock inputs in a chain
The diagram below shows how to link 74192-3 up/down counters with separate up and down clock inputs,
notice how carry and borrow are connected to the up clock and down clock
inputs respectively of the next counter.
The appropriate output becomes low in response to the BCD (binary coded decimal) input. For example an input of binary 0101 (=5) will make output Q5 low and all other outputs high.
The 7442 is a BCD (binary coded decimal) decoder intended for input values 0 to 9 (0000 to 1001 in binary). With inputs from 10 to 15 (1010 to 1111 in binary) all outputs are high.
Note that the 7442 can be used as a 1-of-8 decoder if input D is held low.
Also see: 74HC4017 and 4017
both are a decade counter and 1-of-10 decoder in a single IC.
Display test and blank input are active-low so they should be high for normal operation. When display test is low all the display segments should light (showing number 8).
If the blank input is low the display will be blank when the count input is zero (0000). This can be used to blank leading zeros when there are several display digits driven by a chain of counters. To achieve this blank output should be connected to blank input of the next display down the chain (the next most significant digit).
The 7447 is intended for BCD (binary coded decimal) which is input values 0 to 9 (0000 to 1001 in binary).
Inputs from 10 to 15 (1010 to 1111 in binary) will light odd display segments but will do no harm.