Gates: 2-input | 3-input |
4-input | 8-input | 4069 NOT |
4049 NOT | 4050 Buffer | 4000
Decade and 4-bit counters: 4017 | 4026 | 4029 | 4510 | 4516 | 4518 | 4520
7-bit, 12-bit & 14-bit counters: 4020 | 4024 | 4040 | 4060
Decoders and display drivers: 4028 | 4511
Also see: 74 Series | Logic Gates |
Counting Circuits |
ICs (chips) (with summary of logic ICs)
Quick links to individual ICs
4000 4060 |
If you are using another reference please be aware that there is some variation in the terms used to describe input pins. I have tried to be logically consistent so the term I have used describes the pin's function when high (true). For example 'disable clock' on the 4026 is often labelled 'clock enable' but this can be confusing because it enables the clock when low (false). An input described as 'active low' is like this, it performs its function when low. If you see a line drawn above a label it means it is active low, for example: (say 'reset-bar').
Datasheets are available from:
This gate has a propagation time which is about 10 times longer than normal so it is not suitable for high speed circuits.
NC = No Connection (a pin that is not used).
* = The AND output (pin 1) is not available on some versions of the 4068.
Outputs: These ICs are unusual because they are capable of driving 74LS gate inputs directly. To do this they must have a +5V supply (74LS supply voltage). The gate output is sufficient to drive four 74LS inputs.
NC = No Connection (a pin that is not used).
Note the unusual arrangement of the power supply pins for these ICs!
Two 3-input NOR gates and a single NOT gate in one package.
NC = No Connection (a pin that is not used).
The reset input should be low (0V) for normal operation (counting 0-9). When high it resets the count to zero (Q0 high). This can be done manually with a switch between reset and +Vs and a 10k resistor between reset and 0V. Counting to less than 9 is achieved by connecting the relevant output (Q0-Q9) to reset, for example to count 0,1,2,3 connect Q4 to reset.
The disable input should be low (0V) for normal operation. When high it disables counting so that clock pulses are ignored and the count is kept constant.
The ÷10 output is high for counts 0-4 and low for 5-9, so it provides an output at 1/10 of the clock frequency. It can be used to drive the clock input of another 4017 (to count the tens).
Example projects:
Heart-shaped badge |
Network Lead Tester
The reset input should be low (0V) for normal operation (counting 0-9). When high it resets the count to zero.
The disable clock input should be low (0V) for normal operation. When high it disables counting so that clock pulses are ignored and the count is kept constant.
The enable display input should be high (+Vs) for normal operation. When low it makes outputs a-g low, giving a blank display. The enable out follows this input but with a brief delay.
The ÷10 output (h in table) is high for counts 0-4 and low for 5-9, so it provides an output at 1/10 of the clock frequency. It can be used to drive the clock input of another 4026 to provide multi-digit counting.
The not 2 output is high unless the count is 2 when it goes low.
Example project:
'Random' flasher for 8 LEDs
This project uses the 4026 in an unconventional way, the outputs a-g and
the ÷10 output (h) are used to flash individual LEDs in a complex
pattern which appears random if not studied too closely!
The count occurs as the clock input becomes high (on the rising-edge). The up/down input determines the direction of counting: high for up, low for down. The state of up/down should be changed when the clock is high.
For normal operation (counting) preset, and carry in should be low.
The binary/decade input selects the type of counter: 4-bit binary (0-15) when high; decade (0-9) when low.
The counter may be preset by placing the desired binary number on the inputs A-D and briefly making the preset input high. There is no reset input, but preset can be used to reset the count to zero if inputs A-D are all low.
Connecting synchronous counters in a chain: please see 4510/16 below.
The count occurs as the clock input becomes high (on the rising-edge). The up/down input determines the direction of counting: high for up, low for down. The state of up/down should be changed when the clock is high.
For normal operation (counting) preset, reset and carry in should be low. When reset is high it resets the count to zero (0000, QA-QD low). The clock input should be low when resetting.
The counter may be preset by placing the desired binary number on the inputs A-D and briefly making the preset input high, the clock input should be low when this happens.
Connecting synchronous counters in a chain
The diagram below shows how to link synchronous counters, notice how all the
clock (CK) inputs are linked. Carry out (CO) feeds carry in (CI) of the next counter.
Carry in (CI) of the first counter should be low for 4029, 4510 and 4516 counters.
Normally a clock signal is connected to the clock input, with the enable input held high. Counting advances as the clock signal becomes high (on the rising-edge). Special arrangements are used if the 4518/20 counters are linked in a chain, as explained below.
For normal operation the reset input should be low, making it high resets the counter to zero (0000, QA-QD low).
Counting to less than the maximum (9 or 15) can be achieved by connecting the appropriate output(s) to the reset input, using an AND gate if necessary. For example to count 0 to 8 connect QA (1) and QD (8) to reset using an AND gate.
Connecting 4518 and 4520 counters in a chain
The diagram below shows how to link 4518 and 4520 counters. Notice how the normal clock inputs are
held low, with the enable inputs being used instead. With this arrangement counting advances as the enable
input becomes low (on the falling-edge) allowing output QD to supply a clock signal to the next counter.
The complete chain is a ripple counter, although the individual counters are synchronous!
If it is essential to have truly synchronous counting a system of logic gates is required, please
see a 4518/20 datasheet for further details.
The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain.
Output Qn is the nth stage of the counter, representing 2n, for example Q4 is 24 = 16 (1/16 of clock frequency) and Q14 is 214 = 16384 (1/16384 of clock frequency). Note that Q2 and Q3 are not available.
The reset input should be low for normal operation (counting). When high it resets the count to zero (all outputs low).
Also see: 4040 (12-bit) and 4060 (14-bit with internal oscillator).
The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain.
Output Qn is the nth stage of the counter, representing 2n, for example Q4 is 24 = 16 (1/16 of clock frequency) and Q7 is 27 = 128 (1/128 of clock frequency).
The reset input should be low for normal operation (counting).
When high it resets the count to zero (all outputs low).
The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain.
Output Qn is the nth stage of the counter, representing 2n, for example Q4 is 24 = 16 (1/16 of clock frequency) and Q12 is 212 = 4096 (1/4096 of clock frequency).
The reset input should be low for normal operation (counting). When high it resets the count to zero (all outputs low).
Also see these 14-bit counters: 4020 and 4060 (includes internal oscillator).
The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain. The clock can be driven directly, or connected to the internal oscillator (see below).
Output Qn is the nth stage of the counter, representing 2n, for example Q4 is 24 = 16 (1/16 of clock frequency) and Q14 is 214 = 16384 (1/16384 of clock frequency). Note that Q1-3 and Q11 are not available.
The reset input should be low for normal operation (counting). When high it resets the count to zero (all outputs low).
The 4060 includes an internal oscillator. The clock signal may be supplied in three ways:
The appropriate output Q0-9 becomes high in response to the BCD (binary coded decimal) input. For example an input of binary 0101 (=5) will make output Q5 high and all other outputs low.
The 4028 is a BCD (binary coded decimal) decoder intended for input values 0 to 9 (0000 to 1001 in binary). With inputs from 10 to 15 (1010 to 1111 in binary) all outputs are low.
Note that the 4028 can be used as a 1-of-8 decoder if input D is held low.
Also see: 4017 (a decade counter and 1-of-10 decoder in a single chip).
Display test and blank input are active-low so they should be high for normal operation. When display test is low all the display segments should light (showing number 8). When blank input is low the display will be blank (all segments off).
The store input should be low for normal operation. When store is high the displayed number is stored internally to give a constant display regardless of any changes which may occur to the inputs A-D.
The 4511 is intended for BCD (binary coded decimal).
Inputs values from 10 to 15 (1010 to 1111 in binary) will give a blank display (all segments off).